Many digital machines or devices, such as computers and servers, require high speed reception of digital data. Accordingly, Input/Output (I/O) circuits must be able to recover digital data from a received signal at a very high data rate. When a digital data signal is received by a receiving system, the clock of the system which generated the data may vary in frequency and phase from the clock of the receiving system. If the receiving circuit does not compensate for these variations, errors will occur in determining the received data. Accordingly, an I/O circuit comprises a Data Recovery Circuit (DRC) that recovers the digital data in the presence of these variations.
Two major DRC architectures are used in existing I/O circuits. One is the phase interpolator (PI) based DRC architecture, found in first and second generation Peripheral Component Interface (PCI)—express I/O circuits. The other architecture is the over-sampling DRC, found in Universal Serial Bus (USB) 2.0 I/O circuits. A PI based DRC adaptively adjusts the receiver reference clock based on the received data phase so that the receiver clock tracks the center of the incoming data eye. In contrast, the over-sampling DRC over-samples the incoming digital data and chooses which sample of the over-sampled data best represents the data.